Click here to return to the VHDL Reference Guide. (last edit: 24. september 2012)

Configuration

A configuration declaration defines how the design hierarchy is linked together during elaboration, by listing the entities and architectures used in place of each component instantiation within an architecture. A configuration may also patch up differences between the names and types of generics and ports of the component and the entity.

Syntax

 configuration ConfigurationName of EntityName is
   Declarations...                 {use, attribute or group}
   for ArchitectureName {of entity named above}
     Use...
     ConfigurationItems
   end for;
 end [configuration] [ConfigurationName];

 ConfigurationItems = {one or more of the following}

 for BlockName                     {a nested block or generate statement}
     Use...
     ConfigurationItems
 end for;

 for InstanceLabel, ... : ComponentName
   [use WhatToUse
     [GenericMap]
     [PortMap] ;]
   [for ArchitectureName {going down the hierarchy}
      Use...
      ConfigurationItems
   end for;]
 end for;

 BlockName = {either}
 BlockLabel
 GenerateLabel(ConstantExpression)
 GenerateLabel(Range)

 WhatToUse = {either}
 entity EntityName[(ArchitectureName)]
 configuration ConfigurationName
 open                              {unconfigured}

Where

See (VHDL) File

Rules

The instance labels in front of the component name can be replaced by others or all. Each component instance can be explicitly configured once only. In the absence of a configuration, component instances get configured by default to use an entity with the same name, port names and port types as the component, and to use the most recently compiled architecture.

Synthesis

Although configurations are relevant and useful for selected which entities and architectures make up the design hierarchy, many synthesis tools do not support them. Instead, write a script to synthesize the correct architectures.

Tips

Put the configurations for a design in a separate file. Write a configuration for the top level test bench (initially an empty configuration). Write a configuration for an architecture only when there exists more than one entity or architecture which can be used for the components in that architecture (i.e. when there are choices to be made), and reference that configuration from a higher level configuration.

Example

  use Work.Types.all;
  entity Top is                      -- Top level H/W description
    port (A, B: in Int8; F, G: out Int8);
  end Top;

  architecture Structure of Top is
    component Blk 
      port (A: in Int8; F: out Int8);
    end component;
  begin
    B1: Blk port map (A, F);
    B2: Blk port map (B, G);
  end Structure;

  use Work.Types.all;
  entity Blk is                      -- Pre-synthesis
    port (A: in Int8; F: out Int8);
  end Blk;

  architecture RTL of Blk is
  begin
    ...
  end RTL;

library IEEE;
use IEEE.Std_logic_1164.all;
entity GateLevelBlk is -- Post-synthesis
  port (IP: in  Std_logic_vector(7 downto 0);
        OP: out Std_logic_vector(7 downto 0));
end GateLevelBlk;

architecture Synth of GateLevelBlk is
begin
  ...
end Synth;

use Work.Types.all;
configuration TopMixed of Top is
  for Structure
    for B1: Blk
      use entity Work.Blk(RTL);
    end for;
    for B2: Blk
      use entity Work.GateLevelBlk(Synth)
        port map (IP => To_Vector(A),
                  To_Int8(OP) => F);
    end for;
  end for;
end TopMixed;

use Work.Types.all;
entity Test is            -- Test bench for Top
end Test;

architecture Bench of Test is
  component Top
    port (A, B: in Int8; F, G: out Int8);
  end component;
  signal A, B, F, G: Int8;
begin
  ...
  Inst: Top port map (A, B, F, G);
end Bench;

configuration TestMixed of Test is
  for Bench
    for all: Top
      use configuration Work.TopMixed;
    end for;
  end fo